Saturday, March 15, 2014

Verilog programs 00 : Half adder



Verilog code for a half adder is given below

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//////////////////////////////////////////////////////////////////////////////////
// Website:         www.technoburst.net
// Engineer:        Anil C S
// Create Date:     14:16:21 01/17/2014 
// Design Name:     Verilog basic modules development
// Module Name:     half_adder  
// Description:     Verilog half adder module
// Dependencies:    None
//////////////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ps

module half_adder (input IN1,IN2,output SUM,COUT);
  xor xor_inst1 (SUM,IN1,IN2);
  and and_inst1 (COUT,IN1,IN2);
endmodule

Verilog code of test bench for half adder is shown below

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//////////////////////////////////////////////////////////////////////////////////
// Website:         www.technoburst.net 
// Engineer:        Anil C S
// Create Date:     14:16:21 01/17/2014 
// Design Name:     Verilog basic modules development
// Module Name:     half_adder_test  
// Description:     Verilog half adder module test bench
// Dependencies:    None
//////////////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ps

module half_adder_test;
  
  reg IN1,IN2;
  wire SUM,COUT;
  
  half_adder inst1(.IN1(IN1),.IN2(IN2),.SUM(SUM),.COUT(COUT));
  
  initial begin    
  $display ($time,"\tIN1\tIN2\tSUM\tCOUT");

  #10 IN1=0;IN2=0;
  #10 IN1=0;IN2=1;
  #10 IN1=1;IN2=0;
  #10 IN1=1;IN2=1;
end

initial $monitor($time,"\t%b\t%b\t%b\t%b",IN1,IN2,SUM,COUT);

endmodule

Test bench simulation output is shown below.



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