Saturday, March 8, 2014

Effect of gate propagation delay in SR latch

Gate propagation delays in logic gates are of prime importance in digital design. If these gate propagation delays are left unhandled the results can be catastrophic. Given below is a verilog simulation of NOR gate based SR latch. Initially SR latch is simulated ignoring the gate propagation delays.ModelSim simulation output is given below followed by simulation waveform.



0 S=0 R=0 Q=x QBAR=x
20 S=1 R=0 Q=1 QBAR=0
40 S=0 R=0 Q=1 QBAR=0
60 S=0 R=1 Q=0 QBAR=1
80 S=0 R=0 Q=0 QBAR=1

SR Latch simulation waveform
In the above case, the results are quite fine. Simulation output strictly follows SR latch truth table. Now let us modify the gates in SR latch with a propagation delay of 5ns. Again we simulate SR Latch with the same testbench which we used for the first case. Simlation outputs are presented below.

0   S=0 R=0 Q=x QBAR=x
20  S=1 R=0 Q=x QBAR=x
25  S=1 R=0 Q=x QBAR=0
30  S=1 R=0 Q=1 QBAR=0
40  S=0 R=0 Q=1 QBAR=0
60  S=0 R=1 Q=1 QBAR=0
65  S=0 R=1 Q=0 QBAR=0
70  S=0 R=1 Q=0 QBAR=1
 80  S=0 R=0 Q=0 QBAR=1 

SR latch with gate propagation delay simulation waveform

From the above simulation output, following observations are made.
  • Outputs do not change instantaneously with input
  • SR latch passes through some intermediate states before reaching the final state
  • Presence of forbidden states
  • More output transitions than expected.
Listing below shows analysis of the final simulation with gate propagation delay.

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